Often, memory systems use a bridge chip topology for translating commands associated with one protocol to another protocol associated with a drive being utilized. Typical bridge device topologies include a bridge coupled to a drive. In these cases, the single bridge typically supports multiple output devices on multiple ports.
If the drive is much faster than the bridge, then the performance of the drive is limited by the bridge and a single drive unit will not see the performance of the drive. Rather, the unit will see the performance of the bridge. There is thus a need for addressing these and/or other issues associated with the prior art.